-------------------------------------------------------------------------------
-- SD Card Decoder CPLD
-- Copyright (c) 2009, Takahide Matsutsuka.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
--    notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
--    copyright notice, this list of conditions and the following
--    disclaimer in the documentation and/or other materials provided
--    with the distribution.
-- 3. The name of the author may not be used to endorse or promote
--    products derived from this software without specific prior
--    written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- $Id: SDDecoder.vhd,v 1.2 2009-07-13 16:32:45 markn Exp $
--
-------------------------------------------------------------------------------
-- Create Date:    00:00:00 10/02/2009 
-- Module Name:    SDDecoder - Behavioral 
-- Target Devices: XC9536XL
-- Tool versions:  Xilinx WebPack 9.2i
-- Description:    Decoder/Latch for AVR-SD adapter card for PC-6001
--
-- Dependencies:   This file is a part of SDOS project.
--
-- 11/02/2009 Version 1.0.0 Single 8-bit latch
-- 09/04/2009 Version 1.0.1 Double 8-bit latches
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SDDecoder is
  Port (
    -- PC
    Address15:	in std_logic;
    Address14:	in std_logic;
    AddressL:	in std_logic_vector(7 downto 4);
    DataPC:     inout std_logic_vector(7 downto 0) bus;

    MREQ:       in std_logic;		-- ^Memory request
    IORQ:       in std_logic;		-- ^I/O request
    RD:         in std_logic;		-- ^Read request for SRAM/IO
    WR:         in std_logic;		-- ^Write request for SRAM/IO
    INIT:       in std_logic;		-- ^Reset
    
    -- internal bus
    DataSD:     inout std_logic_vector(7 downto 0) bus;	-- Data bus
    
    -- AVR
    AVRWR:      in std_logic;		-- ^AVR write request
    AVRRD:      in std_logic;		-- ^AVR read request
    INT0:       out std_logic;		-- ^INT0 for AVR (Read request)
    INT1:       out std_logic;		-- ^INT1 for AVR (Write request)
    ROME:       out std_logic;		-- ^Enable for boot rom
    
    -- SRAM
    CS:         out std_logic		-- SRAM CS;
    );
end SDDecoder;

architecture Behaviour of SDDecoder is
  signal OUTREG:        std_logic_vector(7 downto 0);
  signal INREG:	        std_logic_vector(7 downto 0);
  signal IOW:    	std_logic;
  signal IOR: 	        std_logic;
  signal IOE:	        std_logic;
  
begin
  -- output: DataPC, DataSD, CS, WE, OE, INT0, INT1 
  IOE <= AddressL(7) or AddressL(6) or AddressL(5) or AddressL(4);
  IOR <= IORQ or IOE or RD;
  IOW <= IORQ or IOE or WR;
  
  INT0 <= IOR;
  INT1 <= IOW;
  ROME <= INIT or RD or MREQ or Address15 or not Address14;

  process (MREQ, Address15, Address14, INIT, WR)
  begin
    if MREQ = '0' and Address15 = '0' and Address14 = '1' then
      if INIT = '1' or WR = '0' then
        CS <= '0';
      else
        CS <= '1';
      end if;
    elsif MREQ = '0' and Address15 = '1' and Address14 = '0' then
      CS <= '0';
    else
      CS <= '1';
    end if;
  end process;
  
  process (AVRWR, AVRRD, DataSD, OUTREG)
  begin
    DataSD <= "ZZZZZZZZ";
    -- AVR to internal register
    if AVRWR = '0' then
      INREG <= DataSD;
      -- Internal register to AVR
    elsif AVRRD = '0' then
      DataSD <= OUTREG;
    end if;
  end process;
  
  process (IOW, IOR, DataPC, INREG)
  begin
    DataPC <= "ZZZZZZZZ";
    -- Internal register to PC
    if IOR = '0' then
      DataPC <= INREG;
      -- PC to internal register
    elsif IOW = '0' then
      OUTREG <= DataPC;
    end if;
  end process;
end Behaviour;